1. Field of the Invention
The present invention relates to a flat panel display (FPD) device, and more particularly, to an apparatus for automatically controlling the frequency and phase of a sampling clock signal of a flat panel display (FPD) system.
2. Description of the Related Art
A monitor with a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) or a flat panel display (FPD), such as a projection TV, receives graphic signals or video signals input from external sources using a sampling clock signal. To correctly receive an input signal, the frequency and phase of the sampling clock signal should be equal to those of the input signal. If an input graphics/video signal and the sampling clock signal do not have the same frequency and phase, the picture quality of a reproduced image can be adversely affected.
FIG. 1 is a block diagram of a conventional apparatus for controlling the display state of a FPD.
Referring to FIG. 1, an analog-digital converter-phase locked loop (ADC-PLL) 101, a digital signal processor 103, and a controller 105 are used to control the display states of the FPD.
The ADC-PLL 101 includes an analog-digital converter (ADC) (not shown) and a phase locked loop (PLL) (not shown). The PLL generates a sampling clock signal, the frequency and phase of which change in response to a first control signal C1 received from the controller 105. The ADC converts an input analog signal into a digital data signal D1 using the sampling clock signal and outputs the digital data signal D1 to the digital signal processor 103.
The digital signal processor 103 performs image processing such as scaling, gamma correction, and dithering, on the digital data signal D1, according to a second control signal C2 received from the controller 105.
The controller 105 receives a display control signal generated by the manipulation of keys by a user and outputs the first control signal C1 and the second control signal C2.
If the sampling clock signal does not change when the phase and frequency of an analog graphic/video signal input to the ADC changes, the picture quality of a corresponding reproduced image can be adversely affected, as described above. In the conventional technique, by appropriately changing the frequency and phase of a sampling clock signal output by the PLL and sampling an input signal using the changed sampling clock signal, such picture quality deterioration can be mitigated. However, in the configuration shown in FIG. 1, a user must directly generate a display control signal to control the display state when watching a screen, which is inconvenient.